1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a vertical MOS transistors.
2) Description of the Prior Art
Current lateral MOS transistor technology uses lithography to define channel length. This limits the channel length control to that of the lithography process. This lithography process control is not as good as deposition techniques.
Vertical junction MOS transistors have a vertical channel region. However, current methods for fabricating vertical transistor do not have acceptable methods to control the channel length. This is even more important as transistors are further scaled down.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,416,3509 (Watanabe) shows a vertical Tx process.
U.S. Pat. No. 5,899,710 (Mukai) shows a TX with gates surrounding the channel region.
U.S. Pat. No. 4,835,586 (Cogan et al.) shows a vertical dual gate process.
U.S. Pat. No. 4,967,245 (Cogan et al.) shows a vertical Tx in a trench.
However, these patents can be further improved upon.
It is an object of the present invention to provide a method for fabricating a vertical MOS transistor.
It is an object of the present invention to provide a method for fabricating a method for fabricating a vertical MOS transistor that has a controllable channel length.
It is an object of the present invention to provide a method for fabricating a method for fabricating a vertical MOS transistor that the channel length is controlled by the channel deposition process.
To accomplish the above objectives, the present invention provides a method of manufacturing a vertical MOS transistor.
The method begins by forming isolation regions in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. We form a dielectric layer over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. The opening at least partially over the active area. We form a gate layer (e.g. conductive layer) in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. The gate opening is defined at least by sidewalls of the conductive layer. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. The insulating layer is removed by an etch selective to the barrier layer and the gate layer. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. We form contacts through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.
The present invention has the benefit of providing a method for fabricating a vertical MOS transistor that has a controllable channel length. The method controls the channel length by the channel deposition process. This is more accurate than conventional lithographical techniques.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.